The present invention relates to a semiconductor device and a method manufacturing the same, and particularly, to a semiconductor device and a manufacturing method thereof in which a device region is formed by using an insulator filled trench isolation technology.
Conventionally, for example, a method called a local oxidation of silicon has been widely used as a device isolation method used in a semiconductor device. This method will be abbreviated as a LOCOS hereinafter. However, in the LOCOS, an oxide film enters into the periphery of a lower portion of a nitride film used for selective oxidation of a silicon substrate and forms a bird's beak. Therefore, an extra area is required for device isolation so that a miniaturized device isolation region required for manufacturing a large scale semiconductor device with a high density cannot be formed.
An insulator filled trench isolation technology developed in the recent years has attracted considerable attention, as a device isolation method which is suitable for realization of high density and high integration level in the generation of semiconductor devices of a minimum line width 0.25 .mu.m and the later generation of more miniaturized semiconductor devices and which will take the place of the device isolation method using the LOCOS.
Next, explanation will be made of problems in forming device regions isolated from each other. Particularly, for the purpose of application to a CMOS circuit, a problem in forming an insulator filled device isolation region will be specifically explained with reference to FIGS. 1A, 1B, and 1C.
As shown in FIG. 1A, isolation trenches are formed on a silicon substrate 1 by using dry etching, and an insulating film is thereafter filled therein. The surface is subjected to chemical mechanical polishing to form device isolation regions 2 in the silicon substrate. The chemical mechanical polishing will be abbreviated as CMP hereinafter.
Next, as shown in FIG. 1B, the surface of the silicon substrate 1 is coated with a resist film 3, and a N-type impurity is ion-implanted to form a N-well 4.
Subsequently, the N-well 4 ion-implanted is covered with a resist (not shown), and a P-type impurity is ion-implanted into a P-well 5. Thus, a well boundary 6 is formed at the center of the bottom portion of a trench 2.
A P-type source/drain diffusion layer 7 of a P-channel MOS transistor is formed by ion-implantation at device regions of the N-well 4 isolated from each other by a device isolation region 2, as hatched by narrow lines in FIG. 1C. Likewise, an N-type source/drain diffusion layer 8 of an N-channel MOS transistor is formed by ion-implantation at device regions of the P-well 5.
When carrying out pattern formation of the well isolation structure described above, an alignment error of the well boundary 6 sometimes occurs due to the alignment accuracy of photolithography and the dependence on the substrate condition. Therefore, there is a problem that the position of the well boundary 6 shifts by a distance equivalent to the alignment error.
In this case, as long as the side walls 9 of the element separation region 2 are formed at a proper angle close to 90.degree. with respect to the surface of the substrate, the position of the well boundary 6 needs only to be within a range of the bottom width of 2.DELTA.x of the trench of the device isolation region, and therefore, an alignment margin of .DELTA.x exists from the center to one side. For example, even if the position of the well boundary is shifted by .DELTA.x to the right, at least a distance equal to the depth of the trench is maintained between the P-well 5 and the P-type diffusion layer 7. Therefore, there will not occur a punch-through phenomenon in which a large current flows between the P-type diffusion layer 7 and the P-well 5 when a source voltage is applied to the P-type diffusion layer 7.
However, as indicated by a broken line 10 in FIG. 1C, if the inclination of the side wall of the device isolation region 2 is loosened due to some reasons in manufacturing steps, the alignment margin is reduced to .DELTA.x.sub.a from .DELTA.x. That is, if the position of the well boundary 6 is shifted by .DELTA.x.sub.b (where .DELTA.x.sub.a .ltoreq..DELTA.x.sub.b .ltoreq..DELTA.x) due to the alignment error, the minimum distance between the P-well 5 and the P-type diffusion layer 7 approximates the distance d, so that the punch-through will be caused.
The term of punch-through means the following. Second conductive type regions are provided at both ends of a first conductive type region, and ohmic electrodes are respectively provided for the second conductive type regions. When a voltage is applied to the ohmic electrodes, the built-in potential generated at the boundaries between the first and second conductive type regions decreases and a large current flows between the ohmic electrodes, if the distance between the second conductive type regions is smaller than a certain value.
In case of the example shown in FIG. 1C, if the isolation distance between the device isolation regions 2 is practically shortened as indicated by d in the figure, a large current flows between the P-well 5 and the P-type diffusion layer 7 of the N-well 4 when a source voltage is applied therebetween.
Next, explanation will be made of factors which loosen the inclination of the side wall of the device isolation region 2.
Conventionally, in case of etching a silicon substrate by dry etching to form trenches for device isolation regions, the inclination angle of the side wall of a trench having an open space is loosened more than that of a trench having no open space, and the hem of the side wall tends to be pulled obviously at the bottom of the trench (which will be called hem-pulling hereinafter).
That is, if trenches of device isolation regions are on a plane semiconductor substrate 1 formed by dry etching with use of an etching mask 11 as shown in FIG. 2A, the inclination angle of the side walls 9 is a proper value close to 90.degree., and fine small device isolation regions can be formed. However, if one of the side walls opposed to each other is situated apart so that an open space is formed in one side of the trench, the inclination angle of the side wall 10 is loosened.
This occurs due to the following grounds. Specifically, in case of dry-etching of silicon, physical and chemical etching of silicon and deposition of reactants formed by the etching take place simultaneously. FIGS. 2A and 2B schematically show the etching procedure of such etching.
As shown in FIG. 2A, when etching a silicon substrate 1 with use of an etching mask 11, reactants 9a are deposited on the peripheral portions of the etching surface and obstacle the etching thereby tapering the side walls 9 of a trench at a certain tapered angle. Since the tapered angle changes depending on the conditions of the dry-etching, the etching conditions should be determined so as to match with the tapered angle in consideration of the phenomenon described above if a desired tapered angle is 85.degree., for example.
In FIG. 2A, since it is difficult to illustrate influences from the reactants 9a with respect to the tapered angle of the side wall 9 obtained in the final stage, the tapered angles in the intermediate stages are illustrated and exaggerated in the figure.
As shown in FIG. 2B, in case of forming a wide trench having an open space in which one of side walls opposed to each other is arranged apart, the deposition amount of reactants 10a is large with respect to the etching depth. Therefore, the side wall 10 of the trench is looser than the narrow trench shown in FIG. 2A even if same etching conditions are used.
FIG. 3 shows an example of a layout including such an open space. The term of the open space means a region where two device isolation regions 2 extending in the lateral direction in the figure intersect one device isolation region 2a extending in the longitudinal direction in the figure. In case of laying two-dimensionally a large number of device isolation regions, a large number of open spaces are formed. As shown in the plan view of FIG. 3, the side wall 10 facing the open space has a looser inclination angle than the side wall 9 facing no open space, so that hem-pulling is thereby caused.
Each of the device isolation regions 2 and 2a shown in FIG. 3 is filled with an insulating film for device isolation. To clarify particularly the state of hem-pulling caused at a side wall of a trench, the plane shapes of the bottoms of trenches are indicated by continuous lines. The same thing applies to the plane views in FIGS. 4 to 7.
An open space is defined as follows. In FIG. 3, the width of device isolation regions 2 and 2a is designed to be a minimum isolation width T.sub.min. Supposing that T.sub.0 &gt;T.sub.min +T is satisfied where T is the width of device regions 7, 8, 8a, and 8b separated from each other by the device isolation regions 2 and 2a and T.sub.0 is the distance between the edges of the device regions 7 and 8b opposed to each other, the isolation trench between the device isolation regions 2a is called an open space of the device region 7.
In the device isolation regions each having an open space, a significant problem is caused particularly in case where a well boundary 6 is formed along the lengthwise direction at the center of the bottom portion of a device isolation region 2 when forming a PN isolation region for a CMOS circuit consisting of a N-well and a P-well as indicated by one-dot chain line in FIG. 3.
A cross-sectional view and a plan view showing a portion to form an open space are shown in FIG. 4, associated with each other. The lower portion of FIG. 4 shows a plan view including a trench of a device isolation region 2a (which will be simply referred to as an open space 2a hereinafter) which forms an open space, and the upper portion of the figure shows a cross-sectional view thereof along a line A--A. In the plan view, the device region 8b opposed to the device region 7 described in the definition of an open space shown in FIG. 3 is omitted.
As shown in FIG. 4, when hem-pulling like the side wall 10 is formed at the side wall 9 of the trench of the device isolation regions 2 (which will be simply called a trench 2) at the open space 2a, a punch-through phenomenon described with reference to FIG. 1C may be caused.
With reference to the A--A cross-sectional view in FIG. 4, the above-mentioned problem will be explained in more details. If the well boundary 6a is shifted by .DELTA.x.sub.b from a predetermined position on the pattern design to the side of the P-type diffusion layer 7 when making mask alignment, the minimum distance between the P-well 5 and the P-type diffusion layer 7 approximates d. In this case, if the P-type diffusion layer 7 is used as a source of a P-channel MOS transistor forming a CMOS circuit, a source voltage of the CMOS circuit is applied to the P-type diffusion layer 7.
If a large voltage is thus applied between the P-well 5 and the P-type diffusion layer 7, punch-through occurs at the minimum distance d. Note that .DELTA.x indicated in the plan view is a margin where no open space 2a exists and corresponds to .DELTA.x explained with reference to FIG. 1C. If a hem-pulling portion as shown at the side wall 10 does not exist at any part of the side wall 9, the problem of punch-through is not caused when the well boundary 6a is shifted to one side from the predetermined position 6 on the pattern design.
If dry-etching conditions are arranged such that the inclination angle of the side wall 10 facing the open space 2a becomes a desired angle (such as 85.degree. described with reference to FIG. 2A) in order to avoid this problem, etching proceeds excessively at the corner portion between the side wall 9 having no open space and the bottom surface of the trench 2, and the cross-sectional shape of the trench 2 becomes anomalous.
If an insulating film to be filled is deposited in the isolation trench 2 thus having an anomalous cross-sectional shape, excellent coverage cannot be attained, leading to a problem that excellent device isolation properties cannot be obtained.
Thus, it is a very difficult problem for existing dry-etching techniques to make the inclination angle of the side walls 9 and 10 correspond to a desired value regardless of presence or absence of an open space 2a.